LOGIC GATES

(5TH SEM ECE HDL)

VERILOG CODE  (ECE HDL )

module (input a_in,b_in,
output not_op,and_op,nand_op,or_op,nor_op,xor_op,xnor_op);
assign not_op=~(a_in);//not_op=~(b_in);
assign and_op=(a_in&b_in);
assign nand_op=~(a_in&b_in);
assign or_op=(a_in|b_in);
assign nor_op=~(a_in|b_in);
assign xor_op=(a_in^b_in);
assign xnor_op=(a_in^b_in);
endmodule


TRUTH TABLE

SIMULATION RESULTS