Verilog Code to Describe Full adder using Dataflow Style 

module fulladder(a_in, b_in, c_in, sum, carry); 
input a_in, b_in,c_in; 
output sum, carry;                                                                               
assign sum = a_in^b_in^c_in; 
assign carry =(a_in & b_in)|(b_in & c_in)|(a_in & c_in); 
endmodule 

Verilog Code to Describe Full adder using Behavioral Style 

module fulladder(abc, sum, carry); 
input [2:0] abc; 
output sum,carry; 
 reg sum,carry; 
always@(abc)
 begin 
 case (abc) 
 3’b000:begin  sum=1’b0; carry=1’b0;end 
 3’b001:begin  sum=1’b1; carry=1’b0;end 
 3’b010:begin  sum=1’b1; carry=1’b0;end 
 3’b011:begin  sum=1’b0; carry=1’b1;end 
 3’b100:begin  sum=1’b1; carry=1’b0;end  
 3’b101:begin  sum=1’b0; carry=1’b1;end 
 3’b110:begin  sum=1’b0; carry=1’b1;end 
 3’b111:begin  sum=1’b1; carry=1’b1;end        
 default: begin sum=1'bz;  carry=1'bz;end  
endcase 
end
 endmodule 

Verilog Code to Describe Full adder using Gate level Style 

module fulladder(a_in, b_in, c_in, sum, carry); 
input a_in,b_in, c_in; 
output sum,carry;  
wire s1, s2, tems3;  
xor x1(s1,a_in,b_in); 
and a1(s2,a_in,b_in); 
xor x2(sum,s1,c_in); 
and a2(s3,s1,c_in); 
or o1(carry,s3,s2); 
endmodule 

Verilog Code to realize 4-bit comparator 

module comparator(a_in, b_in, L_op,g_op,e_op);
input [3:0] a_in;
 input [3:0] b_in;
output L_op;
 output g_op;
 output e_op;
 reg L_op,g_op,e_op;
 always @ (a_in,b_in)
 begin
 if (a_in<b_in)
   L_op=1'b1;
  else
 L_op=1'b0; 
 if (a_in>b_in)
    g_op=1'b1;
 else
 g_op=1'b0;
 if (a_in==b_in)
    e_op=1'b1;
 else
  e_op=1'b0;
 end endmodule

Video link==https://youtu.be/IoRj6wbI9e8

Verilog Code to realize 4-bit binary to gray converter 

module b2g(b_in, g_op);
input [3:0] b_in;
output [3:0] g_op;
assign g_op[3] = b_in[3];
assign g_op[2] = b_in[3] ^ b_in[2];
assign g_op[1] = b_in[2] ^ b_in[1];
assign g_op[0] = b_in[1] ^ b_in[0];
endmodule


Video link==https://youtu.be/n2cRoB9uFt0

8:3 ENCODER without priority

(5TH SEM ECE HDL)

An encoder is a circuit that changes a set of signals into a code. Let’s begin making a 2-to-1 line encoder truth table by reversing the 1-to-2 decoder truth table 

VERILOG CODE  (ECE HDL )

module encoder8_3(en, a_in,  y_op); 
input en;
 input [7:0] a_in; 
output [2:0] y_op; 
 reg [2:0] y_op;
 always @ (a_in,en) 
begin
 if(en==1 )
 y_op =3’bzzz; 
else 
casex (a_in) 
 8'b00000001: y_op = 3'b000;
 8'b0000001x: y_op = 3'b001;
 8'b000001xx: y_op = 3'b010; 
 8'b00001xxx: y_op = 3'b011; 
 8'b0001xxxx: y_op = 3'b100; 
 8'b001xxxxx: y_op = 3'b101; 
 8'b01xxxxxx: y_op = 3'b110;
 8'b1xxxxxxx: y_op = 3'b111;
 default: y_op =3'bxxx; 
endcase
end 
endmodule 

8:3 ENCODER with priority

(5TH SEM ECE HDL)

An encoder is a circuit that changes a set of signals into a code. Let’s begin making a 2-to-1 line encoder truth table by reversing the 1-to-2 decoder truth table 

VERILOG CODE  (ECE HDL )

module encoder8_3(en, a_in,  y_op); 
input en;
 input [7:0] a_in; 
output [2:0] y_op; 
 reg [2:0] y_op;
 always @ (a_in,en) 
begin
 if(en==1 )
 y_op =3’bzzz; 
else 
case (a_in) 
 8'b00000001: y_op = 3'b000;
 8'b00000010: y_op = 3'b001;
 8'b00000100: y_op = 3'b010; 
 8'b00001000: y_op = 3'b011; 
 8'b00010000: y_op = 3'b100; 
 8'b00100000: y_op = 3'b101; 
 8'b01000000: y_op = 3'b110;
 8'b10000000: y_op = 3'b111;
 default: y_op =3'bxxx; 
endcase
end 
endmodule 

TRUTH TABLE