Verilog Code to Describe Full adder using Dataflow Style 

module fulladder(a_in, b_in, c_in, sum, carry); 
input a_in, b_in,c_in; 
output sum, carry;                                                                               
assign sum = a_in^b_in^c_in; 
assign carry =(a_in & b_in)|(b_in & c_in)|(a_in & c_in); 
endmodule 

Verilog Code to Describe Full adder using Behavioral Style 

module fulladder(abc, sum, carry); 
input [2:0] abc; 
output sum,carry; 
 reg sum,carry; 
always@(abc)
 begin 
 case (abc) 
 3’b000:begin  sum=1’b0; carry=1’b0;end 
 3’b001:begin  sum=1’b1; carry=1’b0;end 
 3’b010:begin  sum=1’b1; carry=1’b0;end 
 3’b011:begin  sum=1’b0; carry=1’b1;end 
 3’b100:begin  sum=1’b1; carry=1’b0;end  
 3’b101:begin  sum=1’b0; carry=1’b1;end 
 3’b110:begin  sum=1’b0; carry=1’b1;end 
 3’b111:begin  sum=1’b1; carry=1’b1;end        
 default: begin sum=1'bz;  carry=1'bz;end  
endcase 
end
 endmodule 

Verilog Code to Describe Full adder using Gate level Style 

module fulladder(a_in, b_in, c_in, sum, carry); 
input a_in,b_in, c_in; 
output sum,carry;  
wire s1, s2, tems3;  
xor x1(s1,a_in,b_in); 
and a1(s2,a_in,b_in); 
xor x2(sum,s1,c_in); 
and a2(s3,s1,c_in); 
or o1(carry,s3,s2); 
endmodule