8:3 ENCODER without priority

(5TH SEM ECE HDL)

An encoder is a circuit that changes a set of signals into a code. Let’s begin making a 2-to-1 line encoder truth table by reversing the 1-to-2 decoder truth table 

VERILOG CODE  (ECE HDL )

module encoder8_3(en, a_in,  y_op); 
input en;
 input [7:0] a_in; 
output [2:0] y_op; 
 reg [2:0] y_op;
 always @ (a_in,en) 
begin
 if(en==1 )
 y_op =3’bzzz; 
else 
casex (a_in) 
 8'b00000001: y_op = 3'b000;
 8'b0000001x: y_op = 3'b001;
 8'b000001xx: y_op = 3'b010; 
 8'b00001xxx: y_op = 3'b011; 
 8'b0001xxxx: y_op = 3'b100; 
 8'b001xxxxx: y_op = 3'b101; 
 8'b01xxxxxx: y_op = 3'b110;
 8'b1xxxxxxx: y_op = 3'b111;
 default: y_op =3'bxxx; 
endcase
end 
endmodule